1. Field of the Invention
In general, the present invention relates to a signal-line driving circuit employed in an active-matrix display device such as a liquid-crystal display device, the display device and electronic equipments each employing the display device.
2. Description of the Related Art
An image display device such as a liquid-crystal display device employs a large number of pixel circuits arranged to form a matrix as display cells and controls the light intensity of each of the display cells in accordance with information of an image to be displayed in order to display the image.
In recent years, the development of liquid-crystal display device and the growth of their performance have been becoming remarkable and it becomes possible to apply the liquid-crystal display device to electronic equipments each used for displaying a video signal input thereto or generated thereby as an image or a video in all fields. Examples of the electronic equipments are a TV set, a portable terminal such as a cellular phone or a PDA (Personal Digital Assistant), a digital camera, a notebook personal computer and a video camera.
FIG. 1 is a block diagram roughly showing the configuration of an ordinary liquid-crystal display device 1.
As shown in the block diagram of FIG. 1, the liquid-crystal display device 1 employs an available display section 2, a signal-line driving circuit 3 and a gate-line driving circuit 4. The available display section 2 includes a plurality of pixel circuits arranged on a transparent insulation substrate such as a glass substrate to form a matrix. Each of the pixel circuits has a liquid-crystal cell. Also referred to hereafter as a horizontal driving circuit HDRV or a source driver, the signal-line driving circuit 3 is a circuit for driving signal lines. On the other hand, also referred to hereafter as a vertical driving circuit VDRV or a gate driver, the gate-line driving circuit 4 is a circuit for driving vertical scan lines or gate lines.
As described above, the available display section 2 includes a plurality of pixel circuits arranged to form a matrix and each of the pixel circuits has a liquid-crystal cell not shown in the block diagram of FIG. 1.
In addition, the available display section 2 also has the signal lines driven by the signal-line driving circuit 3 and the gate lines (or the vertical scan lines) driven by the gate-line driving circuit 4. The signal lines are laid out to serve as lines each corresponding to one of the columns of the matrix whereas the gate lines (or the vertical scan lines) are laid out to serve as lines each corresponding to one of the rows of the matrix.
In order to prevent molecules of liquid crystal in the available display section 2 employed in the liquid-crystal display device from deteriorating, it is necessary to apply an AC voltage to the liquid crystal in the display device. An ordinary liquid-crystal display device adopts the so-called polarity inverting operation method of a common constant driving technique or a common inversion driving technique in order to apply the AC voltage also referred to as a common voltage to the liquid crystal.
In accordance with the common constant driving technique, a voltage appearing on a facing electrode exposed to a pixel electrode is fixed at a constant level whereas, relative to the fixed voltage appearing on the facing electrode, a voltage having a positive polarity and a voltage having a negative polarity are applied to the pixel electrode alternately.
In accordance with the common inversion driving technique, on the other hand, while the voltage appearing on the facing electrode is being inverted from a high level to a low level and vice versa, relative to the varying voltage appearing on the facing electrode, a voltage having a positive polarity and a voltage having a negative polarity are applied to the pixel electrode alternately.
To put it in detail, when the voltage appearing on the facing electrode is set at a high level, a voltage having a negative polarity relative to the high level taken as a reference is applied to the pixel electrode. When the voltage appearing on the facing electrode is set at a low level, on the other hand, a voltage having a positive polarity relative to the low level taken as a reference is applied to the pixel electrode.
An output buffer section employed in the signal-line driving circuit 3 is designed for the polarity inverting operations described above.
In order to carry out the polarity inverting operations, the signal-line driving circuit 3 makes use of a rail-to-rail output analog buffer circuit in the output buffer section as described in CMOS, Circuit Design, Layout and Simulation, P661, FIGS. 25 and 49, authored by R. Jacob, Baker Harry, W. Li and David Boyce and/or adopts a configuration utilizing an output selector having switches in the output buffer section as disclosed in Japanese Patent Laid-open No. Hei 10-153986.
FIG. 2 is a block diagram showing a typical configuration of the existing signal-line driving circuit 3 making use of the output selector.
The signal-line driving circuit 3 employs a line buffer 31, a level shifter 32, a selector section 33, a buffer amplifier section 34 and an output selector 35. The line buffer 31 is a buffer used for storing driving data obtained as a result of a parallel-into-serial conversion process as data to be used for driving signal lines. The level shifter 32 is a section for converting the level of the driving data stored in the line buffer 31 into a level according to a driving level. The selector section 33 is a section including a plurality of DACs (digital-into-analog converters) each used for converting driving data supplied by the level shifter 32 from digital data into analog data in accordance with received gradation voltages. The buffer amplifier section 34 is a section for amplifying driving data received from the selector section 33 in order to generate a signal voltage having the positive polarity and a signal voltage having the negative polarity. The output selector 35 is a section for selectively asserting a signal voltage having the positive polarity and a signal voltage having the negative polarity on every 2 adjacent signal lines respectively.
FIG. 3 is a block diagram showing a typical configuration of the buffer amplifier section 34 and the output selector 35 which are employed in the signal-line driving circuit 3 shown in the block diagram of FIG. 2.
To be more specific, FIG. 3 is a block diagram showing an analog output buffer stage included in the signal-line driving circuit 3 as a stage provided for two adjacent channels CH1 and CH2. In actuality, the number of channels of the analog output buffer stage like the one shown in the block diagram of FIG. 3 is at least 100 and signal lines corresponding to these channels are driven by making use of the driving data.
The buffer amplifier section 34 shown in the block diagram of FIG. 3 employs a first amplifier circuit 34-1 and a second amplifier circuit 34-2 which are provided for the two adjacent channels CH1 to CH2. The first amplifier circuit 34-1 is a circuit for driving a signal line SGL1 connected to the channel CH1 or a signal line SGL2 connected to the channel CH2 by supplying a signal voltage with the positive polarity to the selected signal line SGL1 or SGL2. On the other hand, the second amplifier circuit 34-2 is a circuit for driving the signal line SGL1 or the signal line SGL2 by supplying a signal voltage with the negative polarity to the selected signal line SGL1 or SGL2.
The first amplifier circuit 34-1 employs an OTA (Operational Transconductance Amplifier) 34-11 linked to a DAC of the immediately preceding stage by adoption of a cascade connection technique and an OAMP (output amplifier) 34-12.
To put it in detail, the inverting input terminal (or the (−) input terminal) of the OTA 34-11 is connected to an output line of the DAC (DAC_UPPER) whereas the non-inverting input terminal (or the (+) input terminal) of the OTA 34-11 is connected to the output line of the OAMP 34-12. The output line of the OTA 34-11 is connected to the input line of the OTA 34-12.
By the same token, the second amplifier circuit 34-2 employs an OTA (Operational Transconductance Amplifier) 34-21 linked to a DAC of the immediately preceding stage by adoption of a cascade connection technique and an OAMP (output amplifier) 34-22.
To put it in detail, the inverting input terminal (or the (−) input terminal) of the OTA 34-21 is connected to an output line of the DAC (DAC_LOWER) whereas the non-inverting input terminal (or the (+) input terminal) of the OTA 34-21 is connected to the output line of the OAMP 34-22. The output line of the OTA 34-21 is connected to the input line of the OTA 34-22.
The output selector 35 employs a first switch group 35-1 and a second switch group 35-2.
The first switch group 35-1 has a switch SW11 turned on and off in accordance with control according to a signal STR and a switch SW12 turned on and off in accordance with control according to a signal CRS. The switches SW11 and SW12 are controlled to turn on and off in a mutually complementary manner. That is to say, when the switch SW11 is controlled to turn on, the switch SW12 is controlled to turn off and vice versa.
A contact point a of the switch SW11 is connected to the output line of the OAMP 34-12 employed in the first amplifier circuit 34-1 whereas a contact point b of the switch SW11 is connected to the signal line SGL1 linked to the channel CH1.
On the other hand, while a contact point a of the switch SW12 is also connected to the output line of the OAMP 34-12 employed in the first amplifier circuit 34-1, a contact point b of the switch SW12 is connected to the signal line SGL2 linked to the channel CH2.
By the same token, the second switch group 35-2 has a switch SW21 turned on and off in accordance with control according to a signal STR and a switch SW22 turned on and off in accordance with control according to a signal CRS. The switches SW21 and SW22 are turned on and off in a mutually complementary manner. That is to say, when the switch SW21 is controlled to turn on, the switch SW22 is controlled to turn off and vice versa.
A contact point a of the switch SW21 is connected to the output line of the OAMP 34-22 employed in the second amplifier circuit 34-2 whereas a contact point b of the switch SW21 is connected to the signal line SGL2 linked to the channel CH2.
On the other hand, while a contact point a of the switch SW22 is also connected to the output line of the OAMP 34-22 employed in the second amplifier circuit 34-2, a contact point b of the switch SW22 is connected to the signal line SGL1 linked to the channel CH1.
When the switches SW11 and SW21 are controlled to turn on whereas the switches SW12 and SW22 are controlled to turn off, a positive-polarity signal voltage generated by the first amplifier circuit 34-1 is supplied to the signal line SGL1 whereas a negative-polarity signal voltage generated by the second amplifier circuit 34-2 is supplied to the signal line SGL2.
When the switches SW12 and SW22 are controlled to turn on whereas the switches SW11 and SW21 are controlled to turn off, on the other hand, the positive-polarity signal voltage generated by the first amplifier circuit 34-1 is supplied to the signal line SGL2 whereas the negative-polarity signal voltage generated by the second amplifier circuit 34-2 is supplied to the signal line SGL1.